Zhenye Zhao
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BLOCK 042025–26· First author, algorithm and architecture

High-Throughput LDPC Decoder ASIC for NAND Flash

A turbo bit-flipping algorithm and its matching parallel architecture, taken from theory to a working TSMC 65nm tapeout.

Year
2025–26
Role
First author, algorithm and architecture
Status
Live

Fig. 01 · 2025–26

Synthesis and implementation results for the TTGDBF decoder: 65 nm, a 2.8 ns clock, 151.91 K gates, 0.992 mm², 15.87 Gbps, and the area breakdown of each block.
Tables III and IV. 65 nm CMOS, 2.8 ns, 151.91 K gates, 0.992 mm², 15.87 Gbps at RBER 0.003 — 76% more throughput than the two closest decoders at the same process.
NAND flash controllers need LDPC decoding that is fast enough to keep up with the memory and small enough to sit beside it. Existing bit-flipping decoders converge too slowly, and speeding them up costs area.
The Turbo Two-Bit Gradient Descent Bit-Flipping (TTGDBF) algorithm adds two-bit strength and turbo decoding, accelerating convergence by 75.6% over the state-of-the-art UP-GDBF decoder. A matching parallel decoder architecture was implemented end to end in TSMC 65nm CMOS, using Synopsys Design Compiler and Cadence Innovus.
The result is 15.87 Gbps throughput in 0.992 mm², with 55.5% lower hardware complexity and 75.6% higher throughput than UP-GDBF, while holding FER below 1e-7 at 0.003 RBER.
Published in IEEE Transactions on VLSI Systems.
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