Zhenye Zhao
[04]Research· 6 projects

Research projects.

Every project states the problem it addressed, the approach taken, and what the measurement actually showed.

  • [01]2025–26

    High-Throughput LDPC Decoder ASIC for NAND Flash

    First author, algorithm and architecture

    NAND flash controllers need LDPC decoding that is fast enough to keep up with the memory and small enough to sit beside it. Existing bit-flipping decoders converge too slowly, and speeding them up costs area.

    • LDPC
    • Verilog
    • TSMC 65nm
    • Synopsys DC
    • Cadence Innovus
    Read the full write-up

    Fig. 01 · 2025–26

    Synthesis and implementation results for the TTGDBF decoder: 65 nm, a 2.8 ns clock, 151.91 K gates, 0.992 mm², 15.87 Gbps, and the area breakdown of each block.
    Tables III and IV. 65 nm CMOS, 2.8 ns, 151.91 K gates, 0.992 mm², 15.87 Gbps at RBER 0.003 — 76% more throughput than the two closest decoders at the same process.
  • [02]2024–25

    Electro-optical Reed-Muller Decoder

    First author

    Decoders are limited less by arithmetic than by the energy spent moving data between memory and logic. This work asks what happens when the error-correcting decoder stops being a conventional digital circuit.

    • Optoelectronics
    • Reed-Muller codes
    • Analog circuits
    • Compute-in-memory
    Read the full write-up

    Fig. 02 · 2024–25

    Bit error rate comparison between Dumer’s recursive decoder and the proposed electro-optical decoder over an AWGN channel.
    Fig. 3 — BER of the proposed optical decoder against Dumer’s algorithm. For m = 2 and m = 3 the optical implementation tracks the original within about 0.1 dB.
  • [03]2025–26

    LDPC Decoder IP for UFS 2.1 / 4.0

    Co-developed with Rayson HI-TECH (SZ) Co., Ltd.

    Industry IP rather than a paper: encoder and decoder IP for NAND flash memory controllers, developed in collaboration with Rayson HI-TECH (SZ) Co., Ltd.

    • QC-LDPC
    • CUDA
    • Verilog
    • FPGA verification
    • UMC 40nm
    Read the full write-up

    Fig. 03 · 2025–26

    Data path from host to NAND flash: the host connects over PCIe to a UFS 2.1/4.0 controller containing the LDPC engine and flash translation layer, which reaches the NAND array over ONFI.
    The delivered IP sits inside the flash controller, between the host interface and the NAND array.
  • [04]2023–24

    APT Intrusion Detection with Provenance Graphs

    First author, undergraduate thesis

    Advanced persistent threats leave behavioural traces rather than signatures, so the detection problem becomes a graph problem: given a whole-system provenance graph, decide whether an attack is in progress.

    • Graph neural networks
    • UniMP
    • Provenance graphs
    • Python
    Read the full write-up

    Fig. 04 · 2023–24

    A whole-system provenance graph with the detected attack path highlighted in red, running from the initial compromised process through to the exfiltrated file.
    Signature-free detection: the red path is the attack chain the model reconstructs, which an analyst can read directly after detection.
  • [05]2022–23

    RISC-V Five-Stage Pipelined Processor

    Solo project

    A five-stage IF-ID-EX-MEM-WB pipeline, designed and implemented independently in Verilog, with data and control hazards resolved through forwarding paths and branch prediction.

    • Verilog
    • Vivado
    • RISC-V RV32I
    • CoreMark
    Read the full write-up

    Fig. 05 · 2022–23

    The five pipeline stages of an RV32I processor — IF, ID, EX, MEM and WB — with the forwarding paths that remove data and control stalls.
    Forwarding from EX back to ID and IF removes both hazard stalls without adding pipeline stages.
  • [06]2024

    Mathematical Finance Programme, Oxford

    Participant

    A joint programme run with the Mathematical Institute at the University of Oxford, covering mathematical statistics, machine learning, quantitative finance, and frontier results in financial theory.

    • Mathematical statistics
    • Machine learning
    • Quantitative finance
    Read the full write-up

    Fig. 06 · 2024

    A polynomial curve fitted through sampled points by Newton divided-difference interpolation, with the interpolation intervals marked along the horizontal axis.
    Newton divided-difference interpolation — one of the topics covered in the programme.