Zhenye Zhao
Nanjing UniversityNanjing, China

ZhenyeZhao

I design error-correcting decoders for NAND flash and carry them through to a taped-out chip.

Research & publicationsDownload CVContact

Fig. 0 · Turbo bit-flipping decoder

Three parallel fronts sweeping a codeword. Where two cross, the threads exchange soft information, which is the “turbo” in the algorithm.
LAYERS8 research areas
  • Algorithm
    • Error-correcting codes
    • LDPC decoding
  • Architecture
    • Digital IC design
    • ASIC & VLSI architecture
  • Silicon
    • Near-memory computing
    • Compute-in-memory
    • Optoelectronic computing
  • Tooling
    • FPGA prototyping
[01]Profile

Error-correcting decoders, for NAND flash.

Designing a decoder and its hardware together, so that error correction is fast enough to sit inside the memory system rather than beside it.

I work on error-correcting decoders for NAND flash, at the seam between algorithm and architecture. My first-author TVLSI paper sets out a turbo bit-flipping algorithm for LDPC codes and the parallel decoder built around it. It reaches 15.87 Gbps at 0.992 mm² in TSMC 65nm, and converges 75.6% faster than the state of the art at a comparable error rate.
Before that I spent a year on decoders that do not use transistors the way we are used to. An electro-optical Reed-Muller decoder processes log-likelihood ratios in the optical domain and keeps analog circuits for the final decision only. It appeared in IEEE JETCAS. Rather than repeatedly shuttling data across the memory wall, it sidesteps the von Neumann bottleneck.
Underneath both is the same instinct: if the bottleneck is a data movement problem, change the substrate rather than optimise the loop. I have shipped decoder IP for UFS 2.1/4.0 controllers with Rayson HI-TECH, taped out in UMC 40nm and prepared for Samsung 8nm mass production. I have also written GNN models for APT intrusion detection on provenance graphs, as a first-author undergraduate thesis.
I am currently a master's candidate at Nanjing University, and I am applying to PhD programmes in electrical engineering and computer science.
NOW
  • MEng candidate, Integrated Circuit Engineering — Nanjing University
  • Applying to PhD programmes in EE/CS, 2026
[02]Education· 2 degrees

Nanjing University, undergraduate and graduate.

The degrees, the coursework, and the distinctions that came with them.

Nanjing University crest

Institution

Nanjing University

School of Electronic Science and Engineering

  1. Master of Engineering

    Sept 2024 — Jul 2027 · present

    Integrated Circuit Engineering · Nanjing, China

    GPA 85.33 / 100

    Selected coursework

    • Frontiers of Electronic Information
    • Process and Device Characterization of Integrated Circuits
    • SoC Design Methodology
    • Advanced Semiconductor Physics
    • Modern Digital Signal Processing
    • Practices on Software Engineering

  2. Bachelor of Science

    Sept 2020 — Jul 2024

    Computer Science and Technology · Nanjing, China

    GPA 82.60 / 100

    Selected coursework

    • Artificial Intelligence
    • Introduction to Computer Systems
    • Advanced Programming
    • Digital Logic and Computer Organization Experiments
04Honors

  • National Scholarship for Graduate Students

    2026

    Ministry of Education, PRC

    One of 18 master’s national scholarships awarded in the School of Electronic Science and Engineering in 2026, about 1.3% of its 1,400 graduate students. CNY 20,000 a year.

  • Nanjing University Outstanding Graduate Student

    2025

    Nanjing University

    Awarded to the top 15% of graduate students.

  • Graduate First-Class Academic Scholarship

    2025

    Nanjing University

    Top 20% of graduate students. Awarded in both 2024 and 2025.

  • Graduate First-Class Academic Scholarship

    2024

    Nanjing University

    Top 20% of graduate students.

[03]Publications· 4 entries

Papers and patents.

Journal and conference papers, plus granted patents. Figures are lifted from the published versions; links resolve through the DOI.

  • 2026Journal

    High-Throughput LDPC Decoder for NAND Flash: Turbo Two-Bit Gradient Descent Bit-Flipping Algorithm and VLSI Architecture

    Zhenye Zhao, Nai Lai, Jin Sha

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems

    A turbo two-bit gradient descent bit-flipping algorithm for LDPC codes in NAND flash, paired with a parallel decoder architecture and a full ASIC implementation in TSMC 65nm CMOS. Two-bit strength and turbo decoding accelerate convergence by 75.6% over the state of the art. The decoder delivers 15.87 Gbps throughput in 0.992 mm² while holding FER below 1e-7 at 0.003 RBER.

    View via DOI10.1109/TVLSI.2026.3717043

    Journal · 2026

    Synthesis and implementation results for the TTGDBF decoder: 65 nm, a 2.8 ns clock, 151.91 K gates, 0.992 mm², 15.87 Gbps, and the area breakdown of each block.
    Tables III and IV. 65 nm CMOS, 2.8 ns, 151.91 K gates, 0.992 mm², 15.87 Gbps at RBER 0.003 — 76% more throughput than the two closest decoders at the same process.
  • 2026Journal

    Electro-optical Reed-Muller Code Decoders based on integrated Optics

    Zhenye Zhao, Fuhao Yu, Wei Jiang, Jin Sha

    IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 16, No. 1, pp. 115–123

    IC architectures for error-correcting decoders that explore optical and compute-in-memory paradigms to move past the limits of digital implementations. The recursive electro-optical decoder processes LLR signals directly in the optical domain, minimises optoelectronic conversions, and reserves analog circuits for decision-making only, bypassing the von Neumann bottleneck. It shows a gain of at least five orders of magnitude in energy efficiency, with power scaling linearly with codeword length rather than with computational complexity.

    View via DOI10.1109/JETCAS.2025.3624556

    Journal · 2026

    Architecture of the electro-optical RM(m,r) decoder, divided into an optical field and an electronic field across four decoding steps.
    Fig. 1 — Overview of the RM(m,r) decoder architecture. Received LLRs are processed by DLCCs, split into Lu and Lv, and recombined through the optical/electronic split.
  • 2025Patent

    An Integrated Optical Reed-Muller Decoder Chip and Photonic System

    Jin Sha, Zhenye Zhao

    Chinese invention patent CN202411864690.5

    Patent · 2025

    Schematic of the recursive optical decoding loop: LLR optical computation, photoelectric conversion, analog decision, and electro-optic feedback.
    The decoding cycle. Light performs the LLR computation; analog circuitry is reserved for the hard decision, and the result is fed straight back into the next iteration.
  • 2024Thesis

    APT Intrusion Detection based on Whole-system Provenance Graph Embedding

    Zhenye Zhao

    Bachelor's thesis, Department of Computer Science and Technology, Nanjing University

    A GNN encoder-decoder built on UniMP and MLP for dynamic graph learning, enabling real-time APT detection on provenance graphs without predefined signatures. On the DARPA E3-CADETS dataset it reaches 100% recall at 98% accuracy, and reconstructs attack footprints into compact summary graphs for forensic analysis.

    Thesis · 2024

    A provenance graph with the detected attack chain highlighted, and the UniMP + MLP encoder-decoder evaluated on the DARPA E3-CADETS dataset.
    The model reconstructs the attack chain rather than only raising an alarm, so the finding can be read after detection.
[04]Research· 3 featured

Projects, and what they measured.

A new decoding algorithm, the parallel decoder built around it, and the tapeout that followed.

012025–26

High-Throughput LDPC Decoder ASIC for NAND Flash

First author, algorithm and architecture

NAND flash controllers need LDPC decoding that is fast enough to keep up with the memory and small enough to sit beside it. Existing bit-flipping decoders converge too slowly, and speeding them up costs area.

The Turbo Two-Bit Gradient Descent Bit-Flipping (TTGDBF) algorithm adds two-bit strength and turbo decoding, accelerating convergence by 75.6% over the state-of-the-art UP-GDBF decoder. A matching parallel decoder architecture was implemented end to end in TSMC 65nm CMOS, using Synopsys Design Compiler and Cadence Innovus.

The result is 15.87 Gbps throughput in 0.992 mm², with 55.5% lower hardware complexity and 75.6% higher throughput than UP-GDBF, while holding FER below 1e-7 at 0.003 RBER.

Published in IEEE Transactions on VLSI Systems.

  • LDPC
  • Verilog
  • TSMC 65nm
  • Synopsys DC
  • Cadence Innovus
Read the full write-up
022024–25

Electro-optical Reed-Muller Decoder

First author

Decoders are limited less by arithmetic than by the energy spent moving data between memory and logic. This work asks what happens when the error-correcting decoder stops being a conventional digital circuit.

The recursive electro-optical decoder processes LLR signals directly in the optical domain, minimises the number of optoelectronic conversions, and uses analog circuits only for decision-making. This bypasses the von Neumann bottleneck instead of optimising around it.

The measured gain is at least five orders of magnitude in energy efficiency over electronic counterparts. The theoretical analysis shows power scaling with codeword length rather than with computational complexity, which is what makes high-throughput, energy-constrained systems practical.

Published in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, and extended by the granted Chinese invention patent CN202411864690.5.

  • Optoelectronics
  • Reed-Muller codes
  • Analog circuits
  • Compute-in-memory
Read the full write-up
032025–26

LDPC Decoder IP for UFS 2.1 / 4.0

Co-developed with Rayson HI-TECH (SZ) Co., Ltd.

Industry IP rather than a paper: encoder and decoder IP for NAND flash memory controllers, developed in collaboration with Rayson HI-TECH (SZ) Co., Ltd.

The work proposed a QC-LDPC hard-decision decoding algorithm that reduced hardware area by 55.5% and improved throughput by 75.6%, and then carried it through the complete ASIC design flow: algorithm and CUDA simulation, RTL implementation, FPGA verification, synthesis, and place-and-route.

The IP taped out on UMC 40nm and is prepared for Samsung 8nm mass production.

  • QC-LDPC
  • CUDA
  • Verilog
  • FPGA verification
  • UMC 40nm
Read the full write-up
Browse all projects
[05]Skills & experience· 20 tools

The tools, and where I picked them up.

Rated by how comfortably I would ship production work unsupervised, not by how many years I have typed the words.

Algorithms & theory

The mathematics the decoder is built on.

  • LDPC & ECC93

    Decoding algorithms and architectures

  • Analog & mixed-signal76

    Optical and CIM decoders

  • Graph neural networks82

    Provenance graph security

Mean

84

Design & verification

RTL through to a board that boots.

  • Verilog / SystemVerilog92

    RTL, assertions, UVM

  • Chisel80

    Scala-embedded RTL

  • VCS / Verdi85

    Simulation and debug

  • Vivado84

    FPGA synthesis and timing

  • FPGA prototyping87

    RTL to working hardware

Mean

86

Silicon flow

Synthesis, place-and-route and memory macros.

  • Digital IC design91

    Synthesis through P&R

  • Design Compiler88

    Synopsys ASIC synthesis

  • Innovus86

    Cadence place-and-route

  • Memory Compiler78

    SRAM macro generation

Mean

86

Implementation

Languages and utilities for modelling and delivery.

  • C / C++90

    Modeling, drivers, algorithms

  • CUDA C82

    Algorithm simulation, bit-level

  • Python86

    Automation, ML, data analysis

  • Java / Qt574

    Tooling and GUIs

  • Matlab80

    Numerical modelling

  • PostgreSQL / MySQL78

    Database systems

  • Git / VS Code90

    Daily workflow

  • LaTeX / Zotero92

    Papers and references

Mean

84

Colours follow the stack

  • Algorithm
  • Architecture
  • Silicon
TIMELINE3 positions
  • Aug 2024 — May 2025

    Research on decoding circuits for emerging computational paradigms

    Nanjing University — School of Electronic Science and Engineering · Nanjing

    Designed IC architectures for error-correcting decoders based on optical and compute-in-memory approaches.

    • Engineered a recursive electro-optical decoder that processes LLR signals in the optical domain and keeps analog circuits only for decision-making.
    • Achieved at least five orders of magnitude in energy efficiency over electronic counterparts, with power scaling linearly with codeword length.
    • Published in IEEE JETCAS as first author; extended by granted patent CN202411864690.5.
  • Jun 2025 — Jun 2026

    High-throughput LDPC decoder ASIC for NAND flash storage

    Nanjing University — School of Electronic Science and Engineering · Nanjing

    First-author work from a new decoding algorithm through to a working integrated circuit.

    • Proposed the TTGDBF algorithm with two-bit strength and turbo decoding, accelerating convergence by 75.6% over the state of the art.
    • Designed the parallel decoder architecture and completed a full ASIC implementation in TSMC 65nm CMOS using Synopsys DC and Cadence Innovus.
    • Reached 15.87 Gbps at 0.992 mm², cutting hardware complexity 55.5% while holding FER below 1e-7.
    • Published in IEEE Transactions on VLSI Systems as first author.
  • Mar 2023 — Sept 2023

    Research assistant — blockchain, zero-knowledge proofs, Byzantine consensus

    GIST Lab, Nanjing University · Nanjing

    Supervised by Prof. Changhai Nie. Literature review and exploratory research on privacy-preserving and fault-tolerant ledgers.

    • Investigated zk-SNARKs and zk-STARKs for blockchain privacy and scalability, supporting the lab’s quality-assurance work.
    • Analysed Byzantine Fault Tolerance protocols and consensus mechanisms for decentralised ledgers.
[07]Journal· 3 entries

Notes from the work.

Engineering write-ups, design decisions, and the occasional thing I got wrong.

Read the journal
[08]Contact

Get in touch.

A question about the work, a paper you disagree with, or a decoding problem that needs solving. I answer all of it.

DIRECT
522024230170@smail.nju.edu.cn
Based in
Nanjing, China
Institution
Nanjing University
Status
Applying to PhD programmes in EE/CS, 2026
Elsewhere