Industry IP rather than a paper: encoder and decoder IP for NAND flash memory controllers, developed in collaboration with Rayson HI-TECH (SZ) Co., Ltd.
The work proposed a QC-LDPC hard-decision decoding algorithm that reduced hardware area by 55.5% and improved throughput by 75.6%, and then carried it through the complete ASIC design flow: algorithm and CUDA simulation, RTL implementation, FPGA verification, synthesis, and place-and-route.
The IP taped out on UMC 40nm and is prepared for Samsung 8nm mass production.