Zhenye Zhao
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BLOCK 042022–23· Solo project

RISC-V Five-Stage Pipelined Processor

An RV32I CPU built from scratch in Verilog, taken to FPGA with a working VGA, keyboard and command-line SoC.

Year
2022–23
Role
Solo project
Status
Archived

Fig. 01 · 2022–23

The five pipeline stages of an RV32I processor — IF, ID, EX, MEM and WB — with the forwarding paths that remove data and control stalls.
Forwarding from EX back to ID and IF removes both hazard stalls without adding pipeline stages.
A five-stage IF-ID-EX-MEM-WB pipeline, designed and implemented independently in Verilog, with data and control hazards resolved through forwarding paths and branch prediction.
VGA, keyboard and clock peripherals were integrated into a complete SoC with command-line interaction in Vivado, alongside C-based software. CoreMark was ported and used for performance evaluation. The point was to understand the hardware and software boundary rather than to chase a benchmark number.